Base for baud rate and timer calculations.
#45000000 CONSTANT _#bus_clock
Very early in the startup routine we test the dynamic ram. To have this happen in a resonable time the boot prom needs to be cached. The minimum cache size is 16 meg. So the boot prom is mapped into a 16 meg region at the start of memory. The rest of the memory areas follow from there.
| From | To | Size | Comment |
|---|---|---|---|
| 0x00000000 | 0x07FFFF | 0x80000 | Boot prom |
| 0x01000000 | 0x1FFFFF | 0x200000 | Application flash |
| 0x02400000 | 0x08FFFF | 0x80000 | Synch static memory |
| 0x02600000 | - | - | Bank memory switch |
| 0x02800000 | - | - | Hardware function |
| 0x02A00000 | - | - | Nram |
| 0x02C00000 | 0x07FFFF | 0x80000 | Dual port memory |
| 0x02E00000 | 0x00FFFF | 0x10000 | function see additional table |
| 0x03000000 | 0x0F00FFF | 0x1000 | Modules base address register, any 4kbyte boundry |
| 0x03080000 | 0x0F00FFF | 0x1000 | Internal ram |
| 0x10000000 | 0x10FFFFFF | 0x1000000 | DRAM1 |
.S .( start MCF5307_constants.html)
$00000000 CONSTANT _#boot_flash_base
$00080000 CONSTANT _#boot_flash_size
$01000000 CONSTANT _#application_flash_base
$00200000 CONSTANT _#application_flash_size
$02000000 CONSTANT _#csbar \ chip select base address register value
$00400000 _#csbar + CONSTANT _#Synch_static_ram_base
$00080000 CONSTANT _#Synch_static_ram_size
There are four banks the last is dealt with by the kernel. The other three are dealt with by the application.
$00618000 _#csbar + CONSTANT _#bank_ram_base
$008000 CONSTANT _#bank_ram_size
$00C00000 _#csbar + CONSTANT _#RTI1000_dual_port_base
$00004000 CONSTANT _#RTI1000_dual_port_size
$00E00000 _#csbar + CONSTANT _#function_data_base
$00000040 CONSTANT _#function_data_size
_prom_kernel_start CONSTANT _#sdram0_base
$01000000 CONSTANT _#sdram0_size
_#sdram0_base CONSTANT _#start_dynamic
$11000000 CONSTANT _#end_dynamic
MBAR ( Module Base Address Register) is set with the code:
#mba _#mbar_valid_bit + # D0 MOV D0 MBAR MOV
Once the MBA is set the registers are located in a specific spot in memory.
$03000000 CONSTANT #mba
\ set to zero on a reset, must be set to one for access
\ to system integration module
$00000001 CONSTANT _#mbar_valid_bit
\ every address has an address modifier associated
\ with it. Setting the following bits [revent access
\ to the system modules in particular address spaces.
\ In this system access is allowed in all spaces.
$00000002 CONSTANT _#mbar_block_user_data
$00000004 CONSTANT _#mbar_block_user_code
$00000008 CONSTANT _#mbar_block_system_data
$00000010 CONSTANT _#mbar_block_system_code
$00000020 CONSTANT _#mbar_block_c/i
$00000040 CONSTANT _#mbar_allow_alternate
Base address of the on board static ram. Set with the instruction:
D0 RAMBAR MOV
Section 6.3.4 talks about reducing power consumption, in our case the on board ram is not used for code so we block code accesses
$03080000 CONSTANT _#rambar_base \ coldfire ram
$00000001 CONSTANT _#rambar_valid
$00000002 CONSTANT _#rambar_block_user_data
$00000004 CONSTANT _#rambar_block_user_code
$00000008 CONSTANT _#rambar_block_system_data
$00000010 CONSTANT _#rambar_block_system_code
$00000020 CONSTANT _#rambar_block_c/i
$00000100 CONSTANT _#rambar_write_protect
$1000 CONSTANT _#rambar_size
The memory space can be divided up into three modes. This system has a lot of memory areas devoted to I/O, the default mode shall be suitable for that type of operation. That is non-cachable. Imprecise is the default mode. If a location access resets an interrupt it must be written to. Read imprecise mode allows multiple reads under some circumstances. Oh how I wish for the simple days, when computers did what they where told.
$80000000 CONSTANT _#cacr_EC \ Enable cache
\ $20000000 CONSTANT _#cacr_ESB \ We don't enable the store buffer, there is no code
\ in non cachable areas
\ $10000000 CONSTANT _#cacr_DPI \ Disable CPUSHL invalidate. Don't use the instruction
\ don't care
\ $08000000 CONSTANT _#cacr_HLCK \ don't use.
$01000000 CONSTANT _#cacr_CINVA \ cache invalidate all, needed to get started
\ $00000400 CONSTANT _#cacr_DNFB \ All code is cached
$00000300 CONSTANT _#cacr_DCM \ Default cache mode, cache-inhibited,imprecise
\ $00000001 CONSTANT _#cacr_DW \ write is allowed
_#sdram0_base CONSTANT _#acr0_address_base
_#sdram0_size 1 - $FF000000 AND 8 RSHIFT CONSTANT _#acr0_address_mask \ will be zero
$8000 CONSTANT _#acr0_enable
$6000 CONSTANT _#acr0_SFIELD \ ignore FC2 when matching
$0020 CONSTANT _#acr0_CM \ cachable, copyback
_#boot_flash_base CONSTANT _#acr1_address_base
_#boot_flash_size 1 - $FF000000 AND 8 RSHIFT CONSTANT _#acr1_address_mask \ will be zero
$8000 CONSTANT _#acr1_enable
$6000 CONSTANT _#acr1_SFIELD \ ignore FC2 when matching
$0020 CONSTANT _#acr1_CM \ cachable, copyback
Describe the 5307 memory map in byte offsets. Names are taken
from the 5307 users manual, but are preceeded with a size code.
b = byte
w = word
l = long
See section 8 of the users manual
Read only register. Read if you want to find out reset reason.
$000 #mba + CONSTANT _breg_RSR
$80 CONSTANT _#rst_hard_reset
$20 CONSTANT _#rst_soft_reset
$001 #mba + CONSTANT _breg_SYPCR
\ doesn't work
$80 CONSTANT _#sypcr_watchdog_enable
$40 CONSTANT _#sypcr_timeout_reset
$20 CONSTANT _#sypcr_prescale \ clock divided by 512
\ See table User's manual table 8-5 for the timeout period
\ software watchdog interrupt vector register
$002 #mba + CONSTANT _breg_SWIVR
\ Software watchdog service register
$003 #mba + CONSTANT _breg_SWSR
\ Pin assignment register
\ see section 10 of the users manual see also
\ _wreg_PADDR and _wreg_PADAT
$004 #mba + CONSTANT _wreg_PAR
$07F CONSTANT _#par_value
\ Interrupt assignment register
$006 #mba + CONSTANT _breg_IRQPAR
\ PLL control register
$008 #mba + CONSTANT _breg_PLLCR
$80 CONSTANT _#pllcr_ENBSTOP \ enable stop
07 4 LSHIFT CONSTANT _#pllcr_PLLIPL
\ master bus control register
$00C #mba + CONSTANT _breg_MPARP
$20 CONSTANT _#mpark_IARBCTRL
$10 CONSTANT _#mpark_EARBCTRL
$08 CONSTANT _#mpark_SHOWDATA
See section 8.3.3 of the user manual
| source | AVEC | Level | IP | Vector | comment | |
|---|---|---|---|---|---|---|
| SWT | 0 | 7 | 00 | 40 | ||
| Timer 1 | 1 | 4 | 00 | 1C | 10 msec | |
| Timer 2 | 1 | 6 | 11 | 1E | user | |
| MBUS | 1 | 2 | 11 | 1A | Not used | |
| UART1 | 0 | 5 | 01 | 60 | ||
| UART2 | 0 | 4 | 01 | 61 | ||
| DMA0 | 0 | 6 | 01 | 62 | User | |
| DMA1 | 0 | 6 | 10 | 63 | User | |
| DMA2 | 0 | 5 | 10 | 64 | Uart1 | |
| DMA3 | 0 | 4 | 10 | 65 | Uart2 | |
| EINT7 | 1 | 7 | - | 1F | Bus error | |
| EINT6 | - | - | - | - | ||
| EINT5 | 1 | 5 | 00 | 1D | Frame2 | |
| EINT4 | - | - | - | - | ||
| EINT3 | 1 | 3 | 00 | 1B | Frame1 | |
| EINT2 | - | - | - | - | ||
| EINT1 | 1 | 1 | 00 | 19 | rti-int | |
A read only register
$040 #mba + CONSTANT _lreg_IPR
You set a bit to disable the interrupt.
$044 #mba + CONSTANT _lreg_IMR
$20000 CONSTANT _#imr_DMA3
$10000 CONSTANT _#imr_DMA2
$08000 CONSTANT _#imr_DMA1
$04000 CONSTANT _#imr_DMA0
$02000 CONSTANT _#imr_UART2
$01000 CONSTANT _#imr_UART1
$00800 CONSTANT _#imr_MBUS
$00400 CONSTANT _#imr_TIMER2
$00200 CONSTANT _#imr_TIMER1
$00100 CONSTANT _#imr_SWT
$00080 CONSTANT _#imr_EINT7
$00040 CONSTANT _#imr_EINT6
$00020 CONSTANT _#imr_EINT5
$00010 CONSTANT _#imr_EINT4
$00008 CONSTANT _#imr_EINT3
$00004 CONSTANT _#imr_EINT2
$00002 CONSTANT _#imr_EINT1
Set to true if the external interrupt is to be auto vectored. In our case external interrupt 1 has to be autovectored, all others are vectored. We don't need an external AS on AVEC.
$04B #mba + CONSTANT _breg_AVCR
$80 CONSTANT _#avec_AVEC7
$40 CONSTANT _#avec_AVEC6
$20 CONSTANT _#avec_AVEC5
$10 CONSTANT _#avec_AVEC4
$08 CONSTANT _#avec_AVEC3
$04 CONSTANT _#avec_AVEC2
$02 CONSTANT _#avec_AVEC1
$01 CONSTANT _#avec_BLK
SWT, not working at the moment. See section 8.3.4
$04C #mba + CONSTANT _breg_ICR0
$00 CONSTANT _#icr0_AVEC
$07 2 LSHIFT CONSTANT _#icr0_IL
$00 CONSTANT _#icr0_IP
TIMER 1
$04D #mba + CONSTANT _breg_ICR1
$80 CONSTANT _#icr1_AVEC
$04 2 LSHIFT CONSTANT _#icr1_IL
$00 CONSTANT _#icr1_IP
TIMER 2
$04E #mba + CONSTANT _breg_ICR2
$80 CONSTANT _#icr2_AVEC
$06 2 LSHIFT CONSTANT _#icr2_IL
$00 CONSTANT _#icr2_IP
MBUS
$04F #mba + CONSTANT _breg_ICR3
$80 CONSTANT _#icr3_AVEC
$02 2 LSHIFT CONSTANT _#icr3_IL
$00 CONSTANT _#icr3_IP
Uart 1
$050 #mba + CONSTANT _breg_ICR4
$00 CONSTANT _#icr4_AVEC
$05 2 LSHIFT CONSTANT _#icr4_IL
$01 CONSTANT _#icr4_IP
Uart 2
$051 #mba + CONSTANT _breg_ICR5
$00 CONSTANT _#icr5_AVEC
$04 2 LSHIFT CONSTANT _#icr5_IL
$01 CONSTANT _#icr5_IP
DMA0
$052 #mba + CONSTANT _breg_ICR6
$00 CONSTANT _#icr6_AVEC
$06 2 LSHIFT CONSTANT _#icr6_IL
$01 CONSTANT _#icr6_IP
DMA1
$053 #mba + CONSTANT _breg_ICR7
$00 CONSTANT _#icr7_AVEC
$06 2 LSHIFT CONSTANT _#icr7_IL
$02 CONSTANT _#icr7_IP
DMA2
$054 #mba + CONSTANT _breg_ICR8
$00 CONSTANT _#icr8_AVEC
$05 2 LSHIFT CONSTANT _#icr8_IL
$03 CONSTANT _#icr8_IP
DMA3
\ Interrupt control register 9
$055 #mba + CONSTANT _breg_ICR9
$00 CONSTANT _#icr9_AVEC
$04 2 LSHIFT CONSTANT _#icr9_IL
$03 CONSTANT _#icr9_IP
Reserved
\ Interrupt control register 10
$056 #mba + CONSTANT _breg_ICR10
$80 CONSTANT _#icr10_AVEC
$03 2 LSHIFT CONSTANT _#icr10_IL
$01 CONSTANT _#icr10_IP
Reserved
\ Interrupt control register 11
$057 #mba + CONSTANT _breg_ICR11
$80 CONSTANT _#icr11_AVEC
$03 2 LSHIFT CONSTANT _#icr11_IL
$00 CONSTANT _#icr11_IP
See section 9 of the users manual
Each CSARx and CSBAR determines the base address of the corresponding chip-select pin. CSAR0 and CSAR1 determine the base addresses from which chip-selects 0 and 1 will be offset, respectively. CSBAR determines the base address from which chip-selects 2 through 7 will be offset.
CSAR0 and CSAR1 are 16-bit read/write registers.
CSBAR is a 8-bit read/write register.
The value stored in each CSAR register corresponds to A[31:16]. The value stored in
the CSBAR register corresponds to A[31:24].
CSAR0, CSAR1 and CSBAR are uninitialized by reset
\ Chip select address register bank0
$080 #mba + CONSTANT _wreg_CSAR0
| Bit | Name | Comment |
|---|---|---|
| 31->16 | BAM - Base address mask | This field defines the chip-select block size through the use of address mask bits. Any set bit masks the corresponding base address register (CSAR) bit (the base address bit becomes a don’t care in the decode). 0 = Corresponding address bit is used in chip select decode 1 = Corresponding address bit is a don’t care in chip select decode |
| 15->9 | Reserved | |
| 8 | WP - Write protect | The WP bit can restrict write accesses to the address range in a CSAR. An attempt to write to the range of addresses specified in a CSAR that has this bit set will result in the appropriate chip-select not being selected. 1 = Only read accesses are allowed 0 = Either read or write accesses are allowed |
| 6 | AM - alternate master | When AM=0 and an alternate master access occurs, SC, SD, UC, and UD are “don’t cares” in the chip-select decode. |
| 5 | C/I = CPU space and Interrupt Acknowledge Cycle mask | CS0, CS1, and CS7 only. Set to one to mask out. |
| 4 | SC = Supervisor Code address space mask | Set to one to mask out. |
| 3 | SD = Supervisor Data address space mask | Set to one to mask out. |
| 2 | UC = User Code address space mask | Set to one to mask out. |
| 1 | UD = User Data address space mask | Set to one to mask out. |
| 4 | V - Valid bit | The Valid bit indicates that the contents of its address register, mask register, and control register are valid. The programmed chip selects do not assert until the V-bit is set (except for CS0 which acts as the global (boot) chip select. |
\ chip select mask register bank0
$084 #mba + CONSTANT _lreg_CSMR0
$00100 CONSTANT _#csmrx_WP \ write protect
$00040 CONSTANT _#csmrx_AM \ alternate master
$00020 CONSTANT _#csmrx_C/I \ No cpu/iack select 1,2 and 7
$00010 CONSTANT _#csmrx_SC \ supervisor code
$00008 CONSTANT _#csmrx_SD \ supervisor data
$00004 CONSTANT _#csmrx_UC \ User code
$00002 CONSTANT _#csmrx_UD \ User data
$00001 CONSTANT _#csmrx_V \ valid bit.
Each CSCR controls the auto acknowledge, external master support, port size, burst capability, and activation of each of the chip-selects.
| Bit | Name | Comment |
|---|---|---|
| 15,14 | Reserved | |
| 13->10 | WS - Wait States | This field defines the number of wait states that will be inserted before an internal transfer acknowledge is generated. If the AA bit is set to 0, TA is asserted by the external system regardless of the number of wait states generated. In that case the external transfer acknowledge will end the cycle. |
| 8 | AA - Auto-Acknowledge Enable | This field controls the assertion of the internal transfer-acknowledge during all accesses that hit in the corresponding chip-select address space. If AA=1, the internal transfer-acknowledge will be asserted at the time determined by the value of WS[3:0]. If AA=0, the Chip-Select Module will not cause the internal transfer acknowledge to be asserted and the cycle will have to be terminated by the external system. |
| 7,6 | PS - Port Size |
This field specifies the width of the data associated with each chip-select.
It determines where data will be driven during write cycles
and where data will be sampled during read cycles. 00 = 32-bit port size - Data sampled and driven on D[31:0] 01 = 8-bit port size - Data sampled and driven on D[31:24] only 10 = 16-bit port size - Data sampled and driven on D[31:16] only 11 = 16-bit port size - Data sampled and driven on D[31:16] only |
| 4 | BSTR - Burst Read Enable | This field specifies the read burst capability of the memory associated with each chip- select. If BSTR=1, all reads from port sizes smaller than the requested transfer size will be bursted, including longword reads from 8 and 16-bit ports, word reads from 8-bit ports as well as line reads from 8-, 16-, and 32-bit ports. If BSTR=0, all reads from port sizes smaller than the requested transfer size will be broken into individual reads that are no larger than the specified port size. For example, a longword read from an 8-bit port would be broken into four individual byte reads. 0 = Break all reads that are larger than the specified port size into individual nonburst reads that are no larger than the specified port size |
| 3 | BSTW - Burst Write Enable | This field specifies the write burst capability of the memory associated with each chip-select. If BSTW=1, all writes to port sizes smaller than the requested transfer size will be bursted, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports as well as line writes to 8-, 16-, and 32-bit ports. If BSTW=0, all writes to port sizes smaller than the requested transfer size will be broken into individual writes that are no larger than the specified port size. For example, a longword write to an 8-bit port would be broken into four individual byte writes. |
| 3 | BEM - Byte Enable Module |
This field specifies the mode of functionality for byte enables.
Certain SRAMs have byte enables that must be asserted during reads
(in addition to writes.) The BEM bit may be set in the relevant
CSCR to provide the appropriate mode of byte enable in support of these
SRAMS. The default mode after reset is 0 for CS7 - CS1 and 1 for CS0. 1 = BE/BWE signals generated for data reads and writes 0 = BWE signals generated for data writes only |
\ chip select control register bank0
\ Boot flash
$08A #mba + CONSTANT _wreg_CSCR0
$2000 CONSTANT _#cscr0_wait_states \ eight wait states
$0100 CONSTANT _#cscrx_AA \ auto acknowledge
$0040 CONSTANT _#cscr0_port_size \ 8 bit
$0020 CONSTANT _#cscrx_BEM \ Byte enable module
$0010 CONSTANT _#cscrx_BSTR \ Burst read enable
$0008 CONSTANT _#cscrx_BSWE \ Burst write enable
\ Chip select address register bank1
\ Application flash
$08C #mba + CONSTANT _wreg_CSAR1
\ chip select mask register bank1
$090 #mba + CONSTANT _lreg_CSMR1
\ chip select control register bank1
$096 #mba + CONSTANT _wreg_CSCR1
$1800 CONSTANT _#cscr1_wait_states \ six wait states
$0080 CONSTANT _#cscr1_port_size \ 16 bit
\ Chip select address register bank2
\ RTI1000 duel port memeory
$098 #mba + CONSTANT _wreg_CSAR2
\ pre 00J20C mask
$098 #mba + CONSTANT _breg_CSBAR
\ chip select mask register bank2
$09C #mba + CONSTANT _lreg_CSMR2
\ chip select control register bank2
$0A2 #mba + CONSTANT _wreg_CSCR2
$0000 CONSTANT _#cscr2_wait_states \ zero wait states
$0000 CONSTANT _#cscr2_port_size \ 32 bit
\ chip select mask register bank3
$0AA #mba + CONSTANT _wreg_CSMR3
\ chip select control register bank3
$0AE #mba + CONSTANT _wreg_CSCR3
$0800 CONSTANT _#cscr3_wait_states \ two wait states
$0080 CONSTANT _#cscr3_port_size \ 16 bit
\ Chip select address register bank6
\ Duel port memory
\ $0C8 #mba + CONSTANT _wreg_CSAR6
\ chip select mask register bank6
\ $0CE #mba + CONSTANT _wreg_CSMR6
\ chip select control register bank6
\ $0D2 #mba + CONSTANT _wreg_CSCR6
\ $0C00 CONSTANT _#cscr6_wait_states \ three wait states
\ $0080 CONSTANT _#cscr6_port_size \ 16 bit
\ Chip select address register bank7
\ System control registers.
\ $0D4 #mba + CONSTANT _wreg_CSAR7
\ chip select mask register bank7
\ $0DA #mba + CONSTANT _wreg_CSMR7
\ chip select control register bank7
\ $0DE #mba + CONSTANT _wreg_CSCR7
\ $0C00 CONSTANT _#cscr7_wait_states \ one wait states
\ $0040 CONSTANT _#cscr7_port_size \ 8 bit
.S .( after _#cscr7_port_size)
See section 11 of the users manual
| Sdram Address Pin | Coldfire Address Pin | ROW ADDRESS | COLUMN ADDRESS |
|---|---|---|---|
| 16 | 16 | 1 | |
| A0 | 15 | 15 | 2 used |
| A1 | 14 | 14 | 3 used |
| A2 | 13 | 13 | 4 used |
| A3 | 12 | 12 | 5 used |
| A4 | 11 | 11 | 6 used |
| A5 | 10 | 10 | 7 used |
| A6 | 9 | 9 | 8 used |
| A7 | 17 | 17 | 16 used |
| A8 | 18 | 18 | 17 |
| A9 | 19 | 19 | 18 |
| A11 | 20 | 20 | 19 |
| A10(precharge command) | 21 | 21 | 20 |
| BA0 | 22 | 22 | 21 |
| BA1 | 23 | 23 | 22 |
| 24 | 24 | 23 | |
| 25 | 25 | 24 |
We are using two 1Meg*16*4 per bank.
Memory chips with a page size below 512 byts are not supported. Chips with a page size greater than 512 bytes will have the page split up and placed all over tha place.
In our arrangment each chip has a page size of 512 bytes but two are used to give us a 32 bit wide data path resulting in a page size of 1024 bytes.
In our example the additional bit multiplexed with the column addess is address bit 16. So the second half of the sdram memory page is found 64k away in the coldfire memory map.
The generation of the required row address is the problem of the memory controller. So the net effect is a few more row address generations when long data structures are being delt with.
We have a 32 bit data path, we therfore don't need address bits 0 and 1 in the column address. Looking at the above table we need coldfire address pin 15 connected to the sdram address pin 0, coldfire address pin 14 to sdram address pin 1 and so on until address pin 9. This deal with address bits 2 to 15. Coldfire address pins 17 to 21 are then connected to the sdram address pins 7 to 11, this deals with address bits 16 ( as part of the column address) to 21. Coldfire address pins 20 and 21 are used as the bank selects.
There is one small complication. In 32 bit mode coldfire address A21 has the precharge command on it, this must be connected to sdram adress pin 10.
| bit | name | Comment | BCM550 |
|---|---|---|---|
| 15 | SO - Synchronous Operation | This bit determines if the SADRAMC is in synchronous operation mode. For synchronous DRAMs, this bit must be set to one. Note that once the part has entered into synchronous operation, it cannot be returned to asynchronous operation except by a reset. | 1 |
| 14 | Reserved | 0 | |
| 13 | NAM - No Address Multiplexing | Some implementations will require external multiplexing support. For instance, if there is an external master accessing the DRAM or if a linear addressing scheme is required the SADRAMC multiplexing may not be sufficient. In these cases, it would be advantageous to prevent the SADRAMC from multiplexing the addresses on a DRAM access. If this bit is set to a 1, the SADRAMC will not multiplex the external address bus to provide column addresses. | 0 |
| 12 | COC - Command On Clock enable | Implementations that utilize external multiplexing must have support for command information to be multiplexed onto the SDRAM address bus. This bit allows the command information to be driven out on what is normally the SDRAM clock enable (SCKE). In this case, the SADRAMC will not support self refresh operation, but external support may be generated. If the COC bit is set, the address command bit information will be generated on the SCKE pin. External multiplexing will be responsible for putting the command information on the proper address bit. | 0 |
| 11 | IS - Initiate Self-refresh command | This bit tells the DRAM controller to send the SELF command to both banks to cause the SDRAMs to enter into low-power self-refresh state where they will remain until the IS bit is cleared. When the IS bit is cleared, the DRAM controller will send the SELFX command to the SDRAMs to tell them to exit the self-refresh state. The refresh counter is suspended while the SDRAMs are in self-refresh. This bit is only relevent if the CPU is to be placed in low power mode. The BCM550 doesn't do this. | 0 |
| 10,9 | RTIM - Refresh TIMing | These bits will determine the timing operation of Auto-Refresh in the SADRAMC. Specifically, it will determine the number of clocks inserted between the REF command and the next possible ACTV command. This same timing is used for both banks of the SADRAMC. This corresponds to tRC in the SDRAM specifications. It is given as 90nsec. 1/45mhz = 22nsec a cycle. Options are 3 and 6cycles, 3 gives 66 nsec, which is too short. 6 gives gives 133 nsec which is heaps. | 01 |
| 8->0 | Refresh Count - RC |
This field controls the frequency of refresh performed by the SADRAMC.
One is added to the value stored in these register locations and
multiplied by 16 bus clocks to determine the refresh period. The
Refresh count is obtained from the SDRAM refresh cycle timing which states: 4096 refresh cycles in 64msecs. 64/4096 = .015625 msec a refresh 1/45mhz = .0000222 msec 0.015625/0.0000222 = 703.125 bus clocks. To convert this to a RC field value, RC = (703.125/16)-1=42.945. You round down as refresh have to be occure faster than minimum. A value of 42 is used. The actual refresh time will be (42 +1)*16/45mhz = 15.28 usec | 00101011 |
\ dram control register
$100 #mba + CONSTANT _wreg_DCR
$8000 CONSTANT _#dcr_syncronous_mode
$0200 CONSTANT _#dcr_refresh_timing
$002A CONSTANT _#dcr_refresh_count
DARRx contain base address compare value and the control bits for both banks 0 and 1 of the DRAM controller. Address and timing are also controlled by bits in the DACRx registers.
| bit | name | Comment | BCM550 | ||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31->18 | BA - Base Address Register | These register bits are used in conjunction with the BAM bits in the DCMR to determine the address range in which the associated bank of DRAM will be located. Each bit is compared with the corresponding address of the bus cycle in progress. If each bit matches, or if bits that do not match are masked in the BAM, the address hits in the associated bank’s DRAM block. | DACR0 0001 0000 0000 00 DACR1 0001 0001 0000 00 | ||||||||||||||||||||||||||||||
| 17,16 | Reserved | 00 | |||||||||||||||||||||||||||||||
| 15 | RE - Refresh Enable | This bit determines if the SADRAMC will generate a refresh cycle to the associated DRAM bank. This bit is reset to zero to ensure that the refresh function is disabled at reset. In the end this bit will be set | 1 | ||||||||||||||||||||||||||||||
| 14 | Reserved | 00 | |||||||||||||||||||||||||||||||
| 13,12 | CASL - Column Address Strobe Latency |
These bits determine how long the data is delayed after the CAS signal (or the read
command) is asserted during a SDRAM access. This data delay corresponds to the tRCD
( 30nsec = 2 cycles) specification in most SDRAMs.
This also implies other timings with respect to the SDRAM.
These include active command to precharge command (tRAS ?? ), precharge command to
active command (tRP 30nsec=2 cycles ), last data input to precharge command (tRWL ??),
and last data out to early precharge (tEP ?? ).
|
01 | ||||||||||||||||||||||||||||||
| 11 | Reserved | 00 | |||||||||||||||||||||||||||||||
| 10,9,8 | CBM - Command and Bank Mux |
Because different SDRAM configurations will cause the bank and column bits to
correspond to different addresses these resources have been made programmable.
These bits will determine the addresses these onto which these functions will be
multiplexed. Table below shows the encoding of these bits.
This encoding along with the address multiplexing scheme handles common
organizations of 16-Mbit SDRAMs, as well as some organizations of 4-Mbit,
and allowing room for future 64-Mbit implementations.
Note that the bank select bits include a base bit and all address bits above.
This is to allow for future implementations of SDRAM that have more than one
bank select bit. The selected value has address line 22 and up used for bank select.
| 100 | ||||||||||||||||||||||||||||||
| 6 | IMRS - Mode Register Set Command | This bit will generate the Mode Register Set (MRS) command to the associated SDRAMs. To use this feature, the base address and mask registers must be set. The associated CBM bits should also be initialized. After the IMRS bit is set, the next access to the address space of the SDRAM will cause the MRS command to that SDRAM to be generated. The address of the access should be selected in order to place the correct mode information on the address pins of the SDRAM. This bit is set to initiate a MRS command. The DRAM controller will clear the bit when the command is finished. Table 11-28 summarizes the function of the IMRS Bit. Any accesses via the IMRS bit should be restricted to be no wider than the port size programmed in the PS bits. | - | ||||||||||||||||||||||||||||||
| 5,4 | PS - Port Size |
These two bits will determine the port size of the associated bank of SDRAM which will
allow for dynamic sizing of the associated accesses.
|
00 | ||||||||||||||||||||||||||||||
| 3 | IP - Initiate Precharge all command | This bit will cause a Precharge All (PALL) command to be generated to the associated SDRAM bank. This is useful in the power up sequence of SDRAMs. In order to use this feature, the base address and mask registers must be set. The associated CBM bits should also be initialized. After the IP bit is set, the next access to the address space of the SDRAM will cause the PALL command to that SDRAM bank to be generated. It is automatically cleared by the DRAM controller after the PALL command is finished. Any accesses via the IP bit should be restricted to be no wider than the port size programmed in the PS bits, otherwise two address cycles will be generated and only one is required. | - | ||||||||||||||||||||||||||||||
| 2 | PM - Page Mode |
This bit determines how the associated SDRAM bank supports page mode operation.
| 1 | ||||||||||||||||||||||||||||||
| 1,0 | Reserved | 00 |
\ address and control register bank 0
$108 #mba + CONSTANT _lreg_DACR0
$00008000 CONSTANT _#dacrx_RE \ Refresh enable
$00001000 CONSTANT _#dacrx_CASL \ Column address strobe latency 01
$00000400 CONSTANT _#dacrx_CBM \ Command and bank mux address line 22 and up
$00000040 CONSTANT _#dacrx_IMRS \ Initiate mode register set
$00000008 CONSTANT _#dacrx_IP \ Initiate precharge all
$00000004 CONSTANT _#dacrx_PM
$00000000 CONSTANT _#dacrx_PS \ Port size 32 bit
\ mask register bank 0
.S .( _#dacrx_PS )
DRAM Controller Mask Registers - DMR0 & DMR1 MBAR+$10C,114. These registers contain bits to mask off the compare function for addresses as well as to control response to certain Transfer Type/Transfer Modifier combinations.
| Bit | Name | Comment | BCM550 | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31->18 | BAM - Base Address Mask | This register bits are provided to allow the user to mask or don't care the associated bit in the Base Address (BA) register. If the bit is zero, the associated address is ignored to generate the DRAM hit. This lets you connect various size DRAMs to the SADRAMC. Each sdram bank is 16meg long | 00 0000 0011 1111 | ||||||||||||||
| 17,9 | Reserved | 00 | |||||||||||||||
| 8 | WP - Write Protect | This bit determines if the associated bank of DRAM is write protected. If the bit is set, write accesses to the block of memory space occupied by the DRAM bank will be ignored by the DRAM Controller. | 0 | ||||||||||||||
| 7->1 | C/I, AM, SC, SD, UC, UD - Address Modifier Masks |
These bits allow the associated type of access to be allowed to access DRAM. Table below
shows the definition of the bits. If the bit is one, the associated access type is
ignored. If the bit is zero, the associated access type is allowed to
hit in the DRAM space.
|
100000 | ||||||||||||||
| 0 | V - Valid | This bit is set to show that the registers that control the associated bank of DRAM have been initialized, and that the DRAM Controller can begin to decode DRAM accesses. | 1 |
$10C #mba + CONSTANT _lreg_DMR0
$00FC0000 CONSTANT _#dmrx_address_mask
$00000040 CONSTANT _#dmrx_addr_modifiers
$00000001 CONSTANT _#dmrx_valid
See bank 0 for full description.
\ address and control register bank1
$110 #mba + CONSTANT _lreg_DACR1
\ mask register bank 1
$114 #mba + CONSTANT _lreg_DMR1
See section 12 of the user's manual
Even if cpu locks up the 10msec interrupt has to continue.
| Bit | Name | Comment | Value |
|---|---|---|---|
| 15->8 | PS - Prescaler Value | The prescaler is programmed to divide the clock input by values (system bus clock/(16 or 1) or clock on TIN pin) from 1 to 256. The binary value 00000000 divides the clock by 1; the value 11111111 divides the clock by 256. | 00001111 ( 0F) |
| 7,6 | CE -Capture Edge and Enable Interrupt |
11 = Capture on any edge and enable interrupt on capture event 10 = Capture on falling edge only and enable interrupt on capture event 01 = Capture on rising edge only and enable interrupt on capture event 00 = Disable interrupt on capture event | 00 |
| 5 | OM - Output Mode |
1 = Toggle output 0 = Active-low pulse for one system bus clock cycle (22ns at 45MHz) | 0 |
| 4 | ORI - Output Reference Interrupt Enable |
1 = Enable interrupt upon reaching the reference value 0 = Disable interrupt for reference reached (does not affect interrupt on capture function) | 1 |
| 3 | FRR - Free Run/Restart |
1 = Restart: Timer count is reset immediately after reaching the reference value 0 = Free run: Timer count continues to increment after reaching the reference value | 1 |
| 2,1 | CLK - Input Clock Source for the Timer |
11 = TIN pin (falling edge) 10 = System bus clock divided by 16. Note that this clock source is not synchronized to the timer; thus successive time-outs may vary slightly in length 01 = System bus clock divided by 1 00 = Stop count | 01 |
| 0 | RST - Reset Timer |
This bit performs a software timer reset similar to that of an external reset, although while
this bit is zero, the other register values can still be written, if necessary. Effectively, a
transition of this bit from one to zero is what resets the register values. The counter/timer/
prescaler will not be clocked unless the timer is enabled. 1 = Enable timer 0 = Reset timer (software reset |
1 |
\ timer1 mode register
$140 #mba + CONSTANT _wreg_TMR1
$0F 8 LSHIFT CONSTANT _#tmr1_PS \ divide by 16
$0000 CONSTANT _#tmr1_CE \ don't use capture mode
$0020 CONSTANT _#tmr1_OM \ pulse output
$0010 CONSTANT _#tmr1_ORI \ interrupt on output
$0008 CONSTANT _#tmr1_FRR \ free running
$0002 CONSTANT _#tmr1_CLK \ system clock
$0001 CONSTANT _#tmr1_RST \ enable timer
.S .( _#tmr1_RST )
1/45000000 * 1 * n * m = .01
n*m = 450000 = 16 * 28125
.S .( before _wreg_TRR1)
$144 #mba + CONSTANT _wreg_TRR1
\ COLDFORTH allows # to indicate decimal value
#28125 CONSTANT _#trr1_value
.S .( before _wreg_TCR1)
$148 #mba + CONSTANT _wreg_TCR1
$14C #mba + CONSTANT _wreg_TCN1
Writing true to the appropiate bit resets he interrupt
$151 #mba + CONSTANT _breg_TER1
01 CONSTANT _#ter1_CAP
02 CONSTANT _#ter1_REF
See section 14 of the users manual
\ register offsets, common code is used to control both uarts
| 00 CONSTANT _#m68_mode
| 04 CONSTANT _#m68_clock_select
| 04 CONSTANT _#m68_status
| 08 CONSTANT _#m68_control
| 0C CONSTANT _#m68_data
| 10 CONSTANT _#m68_aux_control
| 14 CONSTANT _#m68_int_enable
| 14 CONSTANT _#m68_int_state
| 18 CONSTANT _#m68_prescaler_MSB
| 1C CONSTANT _#m68_prescaler_LSB
| 30 CONSTANT _#m68_int_vector
| 34 CONSTANT _#m68_input_port
| 38 CONSTANT _#m68_output_set
| 3C CONSTANT _#m68_output_reset
.S .( _#m68_output_reset)
\ uart1 mode register 1
\ Note the mode registers have the same offset.
\ A write command issued to _breg_UCR1 will reset the
\ register pointer. An access to the mode registers
\ will increment the pointer.
$1C0 #mba + CONSTANT _#m68a_base
_#m68a_base _#m68_mode + CONSTANT _breg_UMR11
_#m68a_base _#m68_mode + CONSTANT _breg_UMR21
\ uart1 status register, read
_#m68a_base _#m68_status + CONSTANT _breg_USR1
\ uart1 clock select register, write
_#m68a_base _#m68_clock_select + CONSTANT _breg_UCSR1
\ uart1 command register
_#m68a_base _#m68_control + CONSTANT _breg_UCR1
\ uart1 receive buffer, read
_#m68a_base _#m68_data + CONSTANT _breg_URB1
\ uart1 transmit buffer, write
_#m68a_base _#m68_data + CONSTANT _breg_UTB1
\ uart1 input port change register, read
_#m68a_base _#m68_aux_control + CONSTANT _breg_UIPCR1
\ uart1 auxilary control register, write
_#m68a_base _#m68_aux_control + CONSTANT _breg_UACR1
\ uart1 interrupt status register, read
_#m68a_base _#m68_int_state + CONSTANT _breg_UISR1
\ uart1 interrupt mask register
_#m68a_base _#m68_int_enable + CONSTANT _breg_UIMR1
\ uart1 baud rate prescaler ( MSB)
_#m68a_base _#m68_prescaler_MSB + CONSTANT UBG11
\ uart1 baud rate prescaler ( LSB)
_#m68a_base _#m68_prescaler_LSB + CONSTANT UBG21
\ uart1 interrupt vector register
_#m68a_base _#m68_int_vector + CONSTANT UIVR1
\ uart1 input port register
_#m68a_base _#m68_input_port + CONSTANT UIP1
\ uart1 output port bit set register
_#m68a_base _#m68_output_set + CONSTANT UOP11
\ uart1 output port bit reset register
_#m68a_base _#m68_output_reset + CONSTANT UOP01
\ uart2 mode register 1
\ Note the mode registers have the same offset.
\ A write command issued to _breg_UCR1 will reset the
\ register pointer. An access to the mode registers
\ will increment the pointer.
$200 #mba + CONSTANT _#m68b_base
_#m68b_base _#m68_mode + CONSTANT _breg_UMR12
_#m68b_base _#m68_mode + CONSTANT _breg_UMR22
\ uart1 status register, read
_#m68b_base _#m68_status + CONSTANT _breg_USR2
\ uart1 clock select register, write
_#m68b_base _#m68_clock_select + CONSTANT _breg_UCSR2
\ uart1 command register
_#m68b_base _#m68_control + CONSTANT _breg_UCR2
\ uart1 receive buffer, read
_#m68b_base _#m68_data + CONSTANT _breg_URB2
\ uart1 transmit buffer, write
_#m68b_base _#m68_data + CONSTANT _breg_UTB2
\ uart1 input port change register, read
_#m68b_base _#m68_aux_control + CONSTANT _breg_UIPCR2
\ uart1 auxilary control register, write
_#m68b_base _#m68_aux_control + CONSTANT _breg_UACR2
\ uart1 interrupt status register, read
_#m68b_base _#m68_int_state + CONSTANT _breg_UISR2
\ uart1 interrupt mask register
_#m68b_base _#m68_int_enable + CONSTANT _breg_UIMR2
\ uart1 baud rate prescaler ( MSB)
_#m68b_base _#m68_prescaler_MSB + CONSTANT UBG12
\ uart1 baud rate prescaler ( LSB)
_#m68b_base _#m68_prescaler_LSB + CONSTANT UBG22
\ uart1 interrupt vector register
_#m68b_base _#m68_int_vector + CONSTANT UIVR2
\ uart1 input port register
_#m68b_base _#m68_input_port + CONSTANT UIP2
\ uart1 output port bit set register
_#m68b_base _#m68_output_set + CONSTANT UOP12
\ uart1 output port bit reset register
_#m68b_base _#m68_output_reset + CONSTANT UOP02
See section 10 of the users manual. See also _wreg_PAR.
\ parallel port data direction register
$244 #mba + CONSTANT _wreg_PADDR
$1A00 CONSTANT _#paddr_value
\ parallet port data register
$248 #mba + CONSTANT _wreg_PADAT
\ Use only the kernel
$2000 CONSTANT _#cold_restart
\ Use startup script
$6000 CONSTANT _#warm_restart
\ Use saved application
$4000 CONSTANT _#normal_restart
\
$0080 CONSTANT _#fpga_ok
$6000 CONSTANT _#restart_method_bits
See section 15 of the users manual.
\ mbus address register
$280 #mba + CONSTANT _breg_MADR
\ mbus frequency register
$284 #mba + CONSTANT _breg_MFDR
\ mbus control register
$288 #mba + CONSTANT _breg_MBCR
\ mbus status register
$28C #mba + CONSTANT _breg_MBSR
\ mbus data register
$290 #mba + CONSTANT _breg_MBDR
See section 13 of the users manual
\ dma0 source address register 1
$300 #mba + CONSTANT _lreg_SAR0
\ dma0 destination address register 1
$304 #mba + CONSTANT _lreg_DAR0
\ dma0 control register
$308 #mba + CONSTANT _wreg_DCR0
8000 CONSTANT _#dcrx_INT \ enable interrupt on termination
4000 CONSTANT _#dcrx_EEXT \ external request
2000 CONSTANT _#dcrx_CS \ cycle steal
1000 CONSTANT _#dcrx_AA \ auto align
0100 CONSTANT _#dcrx_SAA \ single address mode
0080 CONSTANT _#dcrx_S_RW \ one = read
0040 CONSTANT _#dcrx_SINC \ source increment
0008 CONSTANT _#dcrx_DINC \ destination inc
0001 CONSTANT _#dcrx_START \ start
\ dma0 count register
$30C #mba + CONSTANT _wreg_BCR0
\ dma0 status register
$310 #mba + CONSTANT _breg_DSR0
\ dma0 interrupt vector register
$314 #mba + CONSTANT _breg_DIVR0
\ dma1 source address register 1
$340 #mba + CONSTANT _lreg_SAR1
\ dma1 destination address register 1
$344 #mba + CONSTANT _lreg_DAR1
\ dma1 control register
$348 #mba + CONSTANT _wreg_DCR1
0006 CONSTANT _#dcr1_DSZE
0030 CONSTANT _#dcr1_SSZE
\ dma1 count register
$34C #mba + CONSTANT _wreg_BCR1
\ dma1 status register
$350 #mba + CONSTANT _breg_DSR1
\ dma1 interrupt vector register
$354 #mba + CONSTANT _breg_DIVR1
\ dma2 source address register 1
$380 #mba + CONSTANT _lreg_SAR2
\ dma2 destination address register 1
$384 #mba + CONSTANT _lreg_DAR2
\ dma2 control register
$388 #mba + CONSTANT _wreg_DCR2
\ dma2 count register
$38C #mba + CONSTANT _wreg_BCR2
\ dma2 status register
$390 #mba + CONSTANT _breg_DSR2
\ dma2 interrupt vector register
$394 #mba + CONSTANT _breg_DIVR2
\ dma3 source address register 1
$3C0 #mba + CONSTANT _lreg_SAR3
\ dma3 destination address register 1
$3C4 #mba + CONSTANT _lreg_DAR3
\ dma3 control register
$3C8 #mba + CONSTANT _wreg_DCR3
\ dma3 count register
$3CC #mba + CONSTANT _wreg_BCR3
\ dma3 status register
$3D0 #mba + CONSTANT _breg_DSR3
\ dma3 interrupt vector register
$3D4 #mba + CONSTANT _breg_DIVR3
_#function_data_base $01 + CONSTANT _#interrupt_other_cpu_reset
_#function_data_base $03 + CONSTANT _breg_int_reset_bus_error
_#function_data_base $0C + CONSTANT _#bank0_direction
_#function_data_base $0D + CONSTANT _#bank1_direction
_#function_data_base $0E + CONSTANT _#bank2_direction
\ Used by the kernel for terminal and disk services
_#function_data_base $0F + CONSTANT _#bank3_direction
_#function_data_base $10 + CONSTANT _#cpu_I_bank0_claim
_#function_data_base $11 + CONSTANT _#cpu_II_bank0_claim
_#function_data_base $12 + CONSTANT _#cpu_I_bank1_claim
_#function_data_base $13 + CONSTANT _#cpu_II_bank1_claim
_#function_data_base $14 + CONSTANT _#cpu_I_bank2_claim
_#function_data_base $15 + CONSTANT _#cpu_II_bank2_claim
_#function_data_base $16 + CONSTANT _#cpu_I_bank3_claim
_#function_data_base $17 + CONSTANT _#cpu_II_bank3_claim
_#function_data_base $18 + CONSTANT _#interrupt_other_cpu
$60 CONSTANT _#m68a_vector
$61 CONSTANT _#m68b_vector
$62 CONSTANT _#dma0_vector
$63 CONSTANT _#dma1_vector
$64 CONSTANT _#dma2_vector
$65 CONSTANT _#dma3_vector
Describe the cache, needed for cache flushed.
2000 CONSTANT _#cache_size
0010 CONSTANT _#cache_line_size
0004 CONSTANT _#cache_sets
.S .( end MCF5307_constants.html)
\ The kernel checksum can't go at the start because that is where the restart
\ vector is stored. So it is placed at the end,
_prom_kernel_end 4 - EQU _prom_kernel_checksum
_prom_kernel_end 8 - EQU _prom_kernel_count
_prom_kernel_end EQU _prom_dictionary_image_start
_prom_dictionary_image_start
_#dictionary_image_size + EQU _prom_dictionary_image_end
_prom_dictionary_image_start EQU _prom_dictionary_checksum
_prom_dictionary_image_start 4 + EQU _prom_dictionary_count
_prom_kernel_start CONSTANT _interrupt_vectors ( Start of interrupt vectors )
\ Section 3.2.2 of user's manual
_interrupt_vectors 0FFFFF AND 0 ??=
$100000 CONSTANT _#heap_size
_prom_kernel_end EQU _#dictionary_start
80000 _#dictionary_start + EQU _#dictionary_end ( End of user dictionary)
_#dictionary_end EQU RMEM4 ( Start of RAM area )
_#sdram0_base _#sdram0_size _#heap_size - + 1 - EQU RMEM5 ( End of ram area)
100000 EQU _#dictionary_flash_base
60000 EQU _#dictionary_flash_size
\ Buffers must be in non cached area as you must be able to DMA into
\ buffers.
RMEM5 1+ CONSTANT _#heap_start
_#heap_start _#heap_size + CONSTANT _#heap_end