COMBINED ADDRESSING MODEL FOR 8086 PROCESSOR M.L. Gassanenko St.Petersburg Institute for Information and Automatics, St.Petersburg, Russia gml@gym.samson.spb.su This paper describes the combined addressing model used in F32/16 - a highly optimised 32-bit Forth for the 8086 family processors. This model allows to use normal arithmetic operations for address calculations at a negligible run-time cost (6 clocks). The Forth system is designed so that more complicated address conversion is rarely needed. 1. INTRODUCTION It is well-known that 8086 is a 16-bit processor that has a 1Mbyte address space. The addresses are presented in the segment:offset form and the physical address is calculated by the formula: address = segment*16 + offset. So, a native address is a segment:offset pair, a 32-bit value made up of two halves. The physical address is calculated by 8086 with the formula address = segment * 10h + offset. It is evident that the use of standard 32-bit arithmetic operations on such pairs is erratic. A linear address is a 20-bit unsigned number. This number is the same as the physical address. Linear addresses are not supported directly by the 8086 processor. When the processor was designed, the 64K segments were not considered as a severe restriction, but now they are. The numerous 16-bit Forth systems that use several address spaces are at least inelegant. If we wanted to have a 32-bit Forth, there was a problem with address arithmetics: the standard arithmetic algorithms cannot, in general case, be applied to the segment:offset addresses. So, we needed an addressing scheme that should: 1) not waste time calculating the segment and offset from the linear address; use of the native segment:offset form was preferrable; 2) allow normal arithmetic addition and subtraction; probably, multiplication and division too. Since we have 32 bits, and the addressing space may be covered by only 20 bits, we can use additional bits to store some additional information. The information we need to know is: a) was there a carry or borrow to/from the high word? b) how much was carried/borrowed? c) if nothing was carried/borrowed, we want the address to be a segment:offset pair that may be directly used by 8086. 2. THE COMBINED ADDRESSING MODEL The combined addresses allow the use of 32-bit arithmetic operations and in the majority of cases such addresses turn out to be compatible with the native addresses supported by the hardware. Suppose that the bits 16-23 (the low byte of segment) of address are normally set to 0. If they are not zeroes, this means that a carry or borrow from/to the offset happened. Since the 8086 address space is covered by 20 bits, we need 4 bits to accumulate carries/borrows. The remaining 4 bits (20-23) allow to determine whether it was carry or borrow (0000 means carry, 1111 (binary) means borrow). So, if all the addresses generated by the system have zeroes in the low byte of the segment, we may distinguish the addresses compatible with the native form from incompatible ones. And to check this compatibility we have just to test the low byte of the high word. 3. SPECIFICATION OF THE COMBINED ADDRESSING MODEL A combined address has the following format: 31 24 23 20 19 16 15 0 ÉÍÑÍÑÍÑÍËÍÑÍÑÍÑÍËÍÑÍÑÍÑÍËÍÑÍÑÍÑÍËÍÑÍÑÍÑÍËÍÑÍÑÍÑÍËÍÑÍÑÍÑÍËÍÑÍÑÍÑÍ» º p a g e ºunu- ³Bº p a g e - r e l a t i v e º º (page number) º sed³Iº 20 - b i t o f f s e t º ÈÍÏÍÏÍÏÍÊÍÏÍÏÍÏÍÊÍÏÍÏÍÏÍÊÍÏÍÏÍÏÍÊÍÏÍÏÍÏÍÊÍÏÍÏÍÏÍÊÍÏÍÏÍÏÍÊÍÏÍÏÍÏͼ The physical address may be calculated with the following formula: (page + BI) * 1000h + offset The BI bit (Borrow Indicator) is set when the page-relative offset is negative (and therefore could be considered as offset sign); it also indicates that a borrow occured from the page number which therefore should be corrected. Pages are contiguous memory areas that start at 4k-aligned (1000h-aligned) boundaries. So, they are analogous to the 8086 segments with the difference that: 1) they numbers are 8-bit (not 16-bit, as for the segments) 2) page-relative offset ranges from -FFFFFh to FFFFFh (not from 0 to FFFFh, as for the segments) and cover all the address space 3) they are not directly supported by the hardware 4) the elements of large data structures should be aligned to avoid problems with the segment overwrap (when 8086 fetches a word at offset FFFFh, it fetches the first byte at FFFFh, and the second one at 0000h). Note that if the bits 20-23 are zeroes, which is true in most cases, we may consider this address as native and use the Intel formula address = segment * 10h + offset = (page * 100h) * 10h + offset Note also that an address in the linear form is also in the conbined form (with page=0). If you consider the BI bit as the offset sign, you must decrement the page number when you specify a negative offset, e.g. 231FFFFFh means offset -1 from page 24h. Since only 20 bits form the 8086 address and the BI bit is 21st (when we count from 1 rather than 0), you may consider the bit 19 (20th counting from 1) as the offset sign. So, 240FFFFFh also means offset -1 from page 24h (which is the same as offset FFFFFh from page 24h since the address is taken modulo 100000h). There are 1000h representations of the same physical address in the combined form, and therefore the use of arithmetic comparison operators without prior transformations is rarely meaningful. Since the offsets more than 64k are not supported by the hardware, a problem arises when the data element crosses the boundary of the segment calculated from the page number. Generally speaking, this problem may be solved by introducing either special checks or some programming discipline; in F32/16 the discipline is reduced to the requirements that the character strings do not exceed 32k, and that half-cells and cells in large datastructures (ones that exceed 60k) are aligned. The most important point is that results of arithmetic operations which arguments are addresses in the combined form are also addresses in the combined form. The only problem here is that arithmetic operations may invalidate the BI bit. This does not happen if the page-relative offset of the result is in the range from -FFFFFh to FFFFFh (the BI bit is considered as the offset sign). Note that invalidation of the BI bit in e.g. addition may be compensated later by subtraction. Notice that although the bits 21-23 are unused, they are not ignored by the arithmetic operations. 4. THE NORMAL ADDRESSES The normal address format guarantees that there are at least 60k of data in the segment calculated from the page number; the addresses represented in the normal format can be compared. 31 24 23 16 15 12 11 0 ÉÍÑÍÑÍÑÍËÍÑÍÑÍÑÍËÍÑÍÑÍÑÍËÍÑÍÑÍÑÍËÍÑÍÑÍÑÍËÍÑÍÑÍÑÍËÍÑÍÑÍÑÍËÍÑÍÑÍÑÍ» º p a g e º0 0 0 0 0 0 0 0 0 0 0 0º unsigned 12-bit offsetº ÈÍÏÍÏÍÏÍÊÍÏÍÏÍÏÍÊÍÏÍÏÍÏÍÊÍÏÍÏÍÏÍÊÍÏÍÏÍÏÍÊÍÏÍÏÍÏÍÊÍÏÍÏÍÏÍÊÍÏÍÏÍÏͼ In F32/16 the addresses of data fields are always of normal format. Note that maximal offset for a normal form address is 4k-1 (FFFh), and we can guarantee that it is followed by 60k of memory that belongs to the segment calculated from the page number. This explains the digit 60k, a bit strange restriction at the first view, that may often be found in this paper. 5. CONCLUSION F32/16 uses the combined addressing model which allows to combine benefits of both 8086 native segment:offset addressing and linear addressing. The combined address model allows to use normal arithmetic operations for address arithmetics at the cost of (typically) 6 additional 8086 clocks and some restrictions (4k-page alignment instead of 16-bytes paragraph one). In most cases the addresses turn out to be compatible with the native Intel8086 segment:offset form, and these 6 clocks are needed to check this compatibility. If user does not use large (more than 60k) data structures, conversion of a combined form address to the native address form will probably never happen.