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This page is about the experimental results of my researches in the area of microprocessors' architecture for embedded application. The main goal - to create the power favourable architecture. I take into consideration energy expended by programmer to write and debug code and microprocessor's energetics efficiency itself. Further, about two main ideas that I try to combine in one architecture. 		only the picture
Forth Forth as aiming to a simplicity of the software and hardware. Stack machine as a minimum for solving of a general purpose tasks. Stack code - compact, modular and portable. Forth processors as precedent of creation of real microprocessors by small forces. All of this is specially important for development of embedded systems. However, recently in such systems even more often apply digital signal processing (DSP), that requires a heightening of performance.
To achieve performance goals, modern DSPs use a general class of architectural features known as Instruction Level Parallelism (ILP) to exploit the fine-grained parallelism available in most DSP algorithms. In most cases modern DSPs has a non-regular architecture, and consequently is poorly accommodated to automatic creation of an effective code. Another processor type has more regular architecture - Very Long Instruction Word (VLIW). New DSP generation created on this base have an increased performance. The significant successes are reached and in creation of compilers for such processors. As a further step it is possible to consider the new class: transport-triggered architecture (TTA). The key property of TTAs is the visibility of all data transports (within the processor) at the architectural level.

 Instruction Level Parallelism
The concepts of a Forth and TTA are simple and have complementary properties, therefore can be used in the framework of one architecture: sTTAck. You can found information about plans and results of creation of model on VHDL and implementation on FPGA, about the translator of a Forth and about the testing of performances for general purpose and DSP tasks here.
17 june 99 Chapyzhenka Aliaksei drom(at)forth.org.ru